1. Field of the Invention
The present invention relates to image information recording method and apparatus, image information reproducing method and apparatus which are suitable for use in application to an editing method, a digital VTR, a hard disc apparatus, an optical disc apparatus and so on, and an editing method and system.
2. Description of the Related Art
There has been an editing system as shown in FIG. 1 in which video signals recorded on a desired portion of a magnetic tape of a video tape cassette loaded into a reproduction-side VCR can be recorded on a portion succeeding a desired position on a magnetic tape of a video tape cassette loaded into a recording-side VCR.
The editing system shown in FIG. 1 has a reproduction-side VCR 1, a recording-side VCR 10, a reference signal generator 37 for supplying reference signals REF to both of the reproduction-side VCR 1 and the recording-side VCR 10 a switching circuit 38 for selectively supplying video signals reproduced by the reproduction-side VCR 1 and the recording-side VCR 10 to a television monitor 39 and selectively supplying audio signals reproduced by the reproduction-side VCR 1 and the recording-side VCR 10 to an amplifier 40, the television monitor 39 for displaying a video signal from the switching circuit 38 as an image on its screen, the amplifier 40 for amplifying an audio signal from the switching circuit 38, and a loudspeaker 41 for outputting an audio signal from the amplifier 40 as a sound.
The reproduction-side VCR 1 is a reproduction only digital VCR which reproduces digital video and audio data recorded on a magnetic tape of a video tape cassette. The recording-side VCR 10 is a digital VCR which can code recording data and decode reproduced data, i.e., code video and audio data to be recorded and record the same on a magnetic tape of a video tape cassette and reproduce digitally coded video and audio data coded and recorded on a magnetic tape of a video tape cassette.
The reproduction-side VCR 1 has a recording and reproducing head 4 mounted on a rotary drum (not shown), a fixed head 5 for recording longitudinal time code (LTC), a tape transport unit 2 having the rotary drum (not shown), a drive system for transporting a magnetic tape 3, a tape loading mechanism and so on, a servo control circuit 6 for effecting servo control on the drive system of the tape transport unit 2, a reproduction signal-processing circuit 7 for subjecting reproduced video and audio data PAV and reproduction time code PLTC to reproduction processing, a system controller 8 for controlling the servo control circuit 6 and the reproduction signal-processing circuit 7, a console panel 9 used for inputting various commands such as commands for reproduction, recording, rewinding, fast-forwarding and so on by pushing keys (not shown). While only one recording and reproduction head is shown in FIG. 1, description will hereinafter be made on the condition that two recording and reproduction heads are mounted on the rotary drum at an interval of an angle of 180.
The recording-side VCR 10 has a recording signal-processing circuit 11 for effecting various recording processings such as a pre-emphasis on video data PV and audio data PA supplied from the reproduction-side VCR 1, a video encoder 12v for effecting a compression coding processing on the video data RV that are subjected to recording processing by the recording signal-processing circuit 11 and supplied therefrom, an audio encoder 12a for effecting a compression coding processing on the audio data RA that are subjected to recording processing by the recording signal-processing circuit 11 and supplied therefrom, a switching circuit 13 for changing a data path, a recording and reproduction head 15 mounted on a rotary drum (not shown), a fixed head 16 for recording an LTC, a tape transport unit 14 having the rotary drum (not shown), a drive system for traveling a magnetic tape 17, a tape loading mechanism and so on, a servo control circuit 24 for effecting servo control on the drive system of the tape transport unit 14, a video decoder 20v for decoding reproduced video data pav to obtain original video data PV, an audio decoder 21a for decoding reproduced audio data pa to obtain original audio data PA, a reproduction signal-processing circuit 22 for subjecting video data PV and audio data
respectively supplied from the video and audio decoders 20v, 21a to reproduction processings such as de-emphasis and subjecting a time code LTC to reproduction processing, a system controller 23 for controlling the servo control circuit 24 and the reproduction signal-processing circuit 22, a console panel 25 used for inputting various commands such as commands for reproduction, recording, rewinding, fast-forwarding and so on by pushing keys.
The console panel 25 has a switch key 26, a playback key 27, a pause key 28, a stop key 29, a fast forward key 30, a rewind key 31, a recording key 32, a variable-speed playback key 33s, a jog dial 33j, a ten-key pad 34 having keys "0" to "9", an enter key 35 representing "decision", and a liquid crystal display (LCD) 36. The switch key 26 is used to designate the reproduction-side VCR 1 or the recording-side VCR 10 as a VCR to be controlled by the system controller 23 when each of the keys is pressed.
There will be described an operation of recording reproduced video and audio data PV, and PA reproduced a desired amount succeeding a desired position of the magnetic tape 3 of the video tape cassette loaded into the reproduction-side VTR 1, on a portion succeeding a desired position of the magnetic tape 17 of the video tape cassette. Hereinafter, such edition is referred to as "an insertion edition".
Before the insertion edition is carried out, the video and audio data PV and PA to be reproduced by the reproduction-side VCR 1 must be selected and a recording start point on the magnetic tape 17 of the video tape cassette loaded into the recording-side VCR 10 must be designated. The reason for these pre-processings is to obtain an edited result desired by a user by selecting an insert image and designating from which position the insert image is to be inserted.
In pressing the switch key 26 by the user, the system controller 23 recognizes that a command supplied thereto through the console panel 25 is a command used to control the reproduction-side VCR 1. Initially, the user must determine which video and audio data PV and PA recorded on the magnetic tape 3 of the video tape cassette loaded into the reproduction-side VCR 1 are selected as the insert image, i.e., determine which position on the magnetic tape 3 the insert image starts and at which position the insert image ends.
The user can monitor the video and audio data PV and PA reproduced, respectively, by the reproduction-side VCR 1 through the television monitor 39 and the loudspeaker 40 by manually switching the switching circuit 38. Subsequently, the user searches start and end positions of the insert image by operating the playback key 27, the pause key 28, the stop key 29, the fast forward key 30, the rewind key 31, the variable-speed playback key 33s or the jog dial 33j etc. on the console panel 25. The video data PAV reproduced by the reproduction-side VCR 1 are supplied through the switching circuit 38 to the television monitor 39 and displayed as the image on the screen of the television monitor 39. The reproduced audio data PA are supplied to through the switching circuit 38 and the amplifier 40 to the loudspeaker 41 and output therefrom as the sound.
The time code PLTC reproduced by the reproduction-side VCR 1 is supplied to the system controller 23 and converted by the system controller 23 into character data corresponding to time information indicated by the time code PLTC. The character data are supplied to the LCD 36 of the console panel 25 and displayed on a display screen of the LCD 36 as an image representing contents of the time code.
Accordingly, the user can watch the time code displayed on the display screen of the LCD 36 while monitoring the video and audio data PV and PA. Specifically, when the user sees the start of a desired insert image, the user can write a time code thereof being displayed on the LCD 36 on a suitable matter such as a paper. Similarly, the user can write a time code of an end position of the insert image.
The user can monitor the video and audio data PV and PA reproduced by the recording-side VCR 10 through the television monitor 39 and the loudspeaker 40, respectively, by manually switching the switching circuit 38. Subsequently, the user searches start and end positions of the insert image by operating the playback key 27, the pause key 28, the stop key 29, the fast forward key 30, the rewind key 31, the variable-speed playback key 33s or the jog dial 33j etc. on the console panel 25. similarly, the user can write an insertion start position of the insert image on the paper.
In order that the editing system carries out an inserting operation, the user must input time codes of the head and end position of the insert image and a time code of an insert position on the magnetic tape 17 by using the ten-key pad 34 and the enter key 35 of the console panel 25. How to input the time codes is easy. Since the time code is usually displayed by using units of "HH (hour), MM(minute), SS (second) and FF (frame)", it is sufficient to press necessary keys of the ten-key pad 34 in an order of the units and lastly press the enter key 35.
When the three time codes are inputted by the above manner, since the system controller 23 of the recording-side VTR 10 has already recognized a present position of the magnetic tape 3 based on the latest time code PLTC supplied from the reproduction-side VCR 1, the system controller 23 supplies a control signal CON commanding a forward or reverse direction high-speed reproduction to the system controller 8 of the reproduction-side VCR 1. When the control signal CON is supplied to the system controller 8 of the reproduction-side VCR 1, the system controller 8 controls the tape transport unit 2 and the servo control circuit 6 to carry out the forward or reverse direction high-speed reproduction. While the high-speed reproduction is carried out, the system controller 23 of the recording-side VCR 10 monitors the time codes PLTC supplied from the reproduction-side VCR 1. When the system controller 23 recognizes that a value indicated by the time code PLTC supplied from the reproduction-side VCR 1 becomes a value of a time code several-second prior to a value of a time code of the head of the insert image, the system controller 23 supplies the control signal commanding stop of an operation of the reproduction-side VCR 1 to the system controller 8 of the reproduction-side VCR 1 to stop the operation. In this description, the value of the time code several-second prior to the value of the time code of the head of the insert image is referred to as a value of a time code of a position precedent to a position where the operation of the reproduction-side VCR 1 is to be stopped temporarily.
The system controller 23 of the recording-side VCR 10 supplies the control signal CON commanding normal-speed reproduction to the system controller 8 of the reproduction-side VCR 1. Based on the control signal CON, the system controller 8 controls the tape transport unit 2 and the servo control circuit 6 to carry out the normal-speed reproduction. While the normal-speed reproduction is carried out, the system controller 23 of the recording-side VCR 10 monitors the time codes PLTC supplied from the reproduction-side VCR 1. When the system controller 23 recognizes that a value indicated by the time code PLTC supplied from the reproduction-side VCR 1 becomes a value of a time code several-second prior to a value of a time code of the head of the insert image, the system controller 23 supplies the control signal commanding pause of an operation of the reproduction-side VCR 1 to the system controller 8 of the reproduction-side VCR 1 to pause the operation. In this description, several seconds in words "a value of a time code several-second prior to a value of a time code of the head of the insert image" means time from a point when the system controller 23 supplies the control signal commanding reproduction to a point when the reproduction-side VCR 1 actually reproduces data, and time prepared for a portion where previously recorded data and data to be recorded are to be overlapped. A position of the magnetic tape 17 loaded into the recording-side VCR 10, i.e., the insertion start point is automatically set by the processings similar to the above processings.
The system controller 23 of the recording-side VCR 10 supplies the control signal CON commanding start of reproduction to the system controller 8 of the reproduction-side VCR 1 and controls the tape transport unit 14 and the servo control unit 24 to start the reproduction operations. The system controller 23 controls the system controller 8 of the reproduction-side VCR 1 and the servo control circuit 24 of the recording-side VCR 10 by employing the reference signal REF supplied from the reference signal generator 37, thereby synchronizing the reproduction-side VCR 1 and the recording-side VCR 10 with each other.
When the time code PLTC supplied from the reproduction-side VCR 1 becomes the time code representing the head position of the insert image, the system controller 23 of the recording-side VCR 10 supplies the control signal CON to the tape transport unit 14 and control the tape transport unit 14 to start a recording operation. Thus, the video and audio data PV and PA reproduced by the reproduction-side VCR 1 are subjected by the recording signal-processing circuit 11 to the recording processings. The video data RV subjected to the recording processing are supplied to the video encoder 12v and subjected thereby to the compression coding processing. The audio data RA subjected to the recording processing are supplied to the audio encoder 12a and subjected thereby to the compression coding processing.
Compression-coded audio data ra are supplied to the video encoder 12v. The video encoder 12v adds compression-coded video data rv and compression-coded audio data ra with a inner parity and an outer parity, respectively, to convert the same into data series having product codes, further adding the data series with synchronization signals and so on. The video encoder 12v supplies the video and audio data rav through the switching circuit 13 to the recording and reproducing head 15. Thus, the video and audio data rav are recorded on the magnetic head 17 in slant tracks formed on a recording surface thereof.
When the time code PLTC supplied from the reproduction-side VCR 1 becomes the time code indicating the end position of the insert image, the system controller 23 of the recording-side VCR 10 supplies the control signal to the tape transport unit 14 and controls the tape transport unit 14 to stop the recording operation. The system controller 23 of the recording-side VCR 10 supplies the control signal CON commanding the stop of the operation of the reproduction-side VCR 1 to the system controller 8 of the reproduction-side VCR 1. When the system controller 8 of the reproduction-side VCR 1 is supplied with the control signal CON, the system controller 8 supplies the control signal to the tape transport unit 2 and controls the tape transport unit 2 to stop the reproduction operation.
As described above, it is possible to record the video and audio data of a desired portion recorded on the magnetic tape 3 of the video tape cassette loaded into the reproduction-side VCR 1 on the portion succeeding the desired position of the magnetic tape 17 of the video tape cassette.
Subsequently, the video encoder 12v shown in FIG. 1 will be described with reference to FIG. 2. FIG. 2 is a structural diagram showing an inner arrangement of the video encoder 12v shown in FIG. 1.
The video encoder 12v shown in FIG. 2 has an input terminal 50 to which the video data RV are supplied from the recording signal-processing circuit 11 shown in FIG. 1. The input terminal 50 is connected to a first input terminal of a motion detection circuit 51, the other input terminal of a motion compensation circuit 56 and an input terminal of a frame memory 52. An output terminal of the frame memory 52 is connected to a second input terminal of the motion detection circuit 51, an input terminal of a frame memory 54, an addition-side input terminal of an adder circuit 59, the other fixed contact b of a switch 60, and the other input terminal of a inter/intra determining circuit 61. An output terminal of the frame memory 54 is connected to a third input terminal of the motion detection circuit 51 and the other input terminal of a motion compensation circuit 57. An output terminal of the motion compensation circuit 56 is connected to a one addition-side input terminal of the adder circuit 58 having a 1/2 multiplier. An output terminal of a motion compensation circuit 57 is connected to the other addition-side input terminal of the adder circuit 58 having a 1/2 multiplier. An output terminal of the adder circuit 58 is connected to a subtraction-side input terminal of the adder circuit 59. An output terminal of the adder circuit 59 is connected to a fixed contact a of the switch 60 and one input terminal of the inter/intra determining circuit 61. A movable contact c of the switch 60 is connected to an input terminal of a Discrete cosine transform (DCT) circuit 64. An output terminal of the DCT circuit 64 is connected to an input terminal of a quantizing circuit 65. An output terminal of the quantizing circuit 65 is connected to an input terminal of a variable-length coding circuit 66. An output terminal of the variable-length coding circuit 66 is connected to an input terminal of an output coding circuit 68. An output terminal of the output coding circuit 68 is connected through an output terminal 69 of the video encoder 12v to an input terminal of the switching circuit 13 shown in FIG. 1. An output terminal of the motion detection circuit 51 is connected to the respective input terminals of the motion compensation circuits 56, 57 and the input terminal of the variable-length coding circuit 66.
The frame memories 52, 54 read and write image data based on respective read/write control signals supplied thereto from the system controller 23 shown in FIG. 1 through input terminals 53I, 55I.
When frame image data are stored in the frame memory 52, if an output from the frame memory 52 is defined as data of a frame at present, then frame image data supplied to the input terminal 50 are data of a frame in future and an output from the frame memory 54 are data of a frame in past. Hereinafter, a frame at present, a frame in future and a frame in past are referred to as "the present frame", "the succeeding frame" and "the preceding frame", respectively.
The motion detection circuit 51 subjects frame image data supplied through the input terminal 50, frame image data read out from the frame memory 52 and the frame image data read out from the frame memory 54 to motion detection processing by a macro block unit of 16 lines.times.16 pixels. A known motion detection method is a block matching (U.S. Pat. No. 4,897,720).
Specifically, the motion detection circuit 51 carries out motion detection by using macro block data MB (f) of the present frame stored in the frame memory 52 and macro block data MB (f+1) of the succeeding frame supplied through the input terminal 50 to obtain motion vector data MV on the basis of the results of the motion detection. The motion detection circuit 51 carries out motion detection by using the macro block data MB (f) of the present frame stored in the frame memory 52 and macro block data MB (f-1) of the preceding frame stored in the frame memory 54 to obtain motion vector data MV on the basis of results of the motion detection.
While a signal line connected to the output terminal of the motion detection circuit 51 is represented by a single line and one "MV" is used as a reference symbol depicting the motion vector data in FIG. 2, the motion vector data MV of the same number as all the macro blocks of the frame image data stored in the frame memory 52 are calculated in each of the motion detections.
Based on the motion vector data MV supplied from the motion detection circuit 51, the motion compensation circuit 56 extracts the macro black data MB (f+1) most similar to the contents of the macro black data MB (f) being processed of the present frame, from frame image data of the succeeding frame supplied through the input terminal 50. The motion compensation circuit 56 supplies the extracted macro block data MB (f+1) to the adder circuit 58.
Based on the motion vector data MV supplied from the motion detection circuit 51, the motion compensation circuit 57 extracts the macro black data MB (f-1) most similar to the contents of the macro black data MB (f) being processed of the present frame, from frame image data of the preceding frame stored in the frame memory 54. The motion compensation circuit 56 supplies the extracted macro block data MB (f-1) to the adder circuit 58.
The adder circuit 58 add the macro block data MB (f+1) supplied from the motion compensation circuit 56 and the macro block data MB (f-1) supplied from the motion compensation circuit 57 and multiples a result of the addition by a coefficient "1/2" by the 1/2 multiplier provided therein. As a result, the adder obtains a mean value of the macro block data MB (f+1) supplied from the motion compensation circuit 56 and the macro block data MB (f-1) supplied from the motion compensation circuit 57.
The adder circuit 59 subtracts the addition output from the adder circuit 58 from the macro block data MB (f) of the present frame supplied from the frame memory 52, thereby obtaining a difference between the macro block data MB (f) of the present frame and the macro block data obtained by bidirectional prediction.
The inter/intra determining circuit 61 properly connects the movable contact c of the switch 60 to the inter-side fixed contact a or the intra-side fixed contact b based on the difference data supplied from the adder circuit 59, the macro block MB (f) supplied from the frame memory 52 and a frame pulse Fp supplied thereto from the system controller 23 shown in FIG. 1 through an input terminal 62I.
The above description will be summarized. An object to be coded is the frame memory data of the present frame stored in the frame memory 52. A processing unit is a macro block unit. An object of the motion detection processing in the motion detection circuit 51 is to search the respective macro block data MB (f+1) and MB (f-1) of the succeeding and preceding frame most similar to the contents of the macro block MB (f) of the present frame to be coded. A result of the search, i.e., a result of detecting the respective macro block data MB (f+1) and MB (f-1) of the succeeding and preceding frame most similar to the contents of the macro block MB (f) of the present frame is the motion vector data MV. The respective macro block data MB (f+1) and MB (f-1) of the succeeding and preceding frame most similar to the contents of the macro block MB (f) of the present frame are extracted by using the motion vector data MV, thereby common contents being prevented from being transferred.
However, the macro block data MB (f) of the present frame form which the adder circuit 59 calculates difference by using the macro block data obtained by the bidirectional prediction cannot be decoded only with difference data when decoded. Therefore, as shown in FIG. 2, the motion vector data MV are supplied to the variable-length coding circuit 66, compressed by variable-length processing therein and then transferred to the output coding circuit 68 together with the difference data.
A role of the inter/intra determining circuit 61 is to select coding of the difference data and coding of the output from the frame memory 54 as described above. To code the difference data, i.e., difference information between frames is referred to as interframe coding (inter-coding). To code an output from the frame memory is referred to as intraframe coding (intra-coding). "Coding" in the description means not calculation of difference by the adder circuit 59 but coding carried out by circuits, which will be described later, succeeding the DCT circuit 64. While switching inter-coding and intra-coding is controlled by a macro block unit, the switching is controlled by a frame unit in order to facilitate the following description.
The image data of each frame output from the switch 60 and coded by the succeeding circuits is generally referred to as an intra-coded picture (I picture), a bidirectionally predictive-coded picture (B picture) and a predictive-coded picture (P picture) depending on coding state.
The I picture is coded image data of one frame amount formed of data obtained by subjecting the macro block data MB (f) of the present frame output from the switch 60 to intraframe coding. The word "coding" used in the above sentence is coding in the DCT circuit 64, the quantizing circuit 65, and the variable-length coding circuit 66. Accordingly, when the image data is the I picture, the movable contact c of the switch 60 must be connected to the fixed contact b thereof under the control of the inter/intra determining circuit 61.
The P picture is coded image data of one frame amount formed of data obtained by coding difference data between the macro block data MB (f) of the present frame output from the switch 60 and motion-compensated macro block data of I or P picture which is precedent, in view of time, to the macro block data MB (f) of the present frame, and data obtained by subjecting the macro block data MB (f) of the present frame to the intraframe coding. Motion vector data MV used to motion compensate the image data as the I picture when the P picture is generated are calculated from image data to be coded as the P picture and image data immediately prior to the image data in view of an order of image data input to the video encoder 12v.
The B picture is data obtained by coding (interframe coding) difference data between the macro block data MB (f) of the present frame output from the switch 60 and the following six kinds of macro block data.
The six kinds of macro block data are the motion-compensated macro block data of I picture of a frame precedent, in view of time, to the macro block data MB (f) of the present frame, the motion-compensated macro block data of P picture of a frame precedent, in view of time, to the macro block data MB (f) of the present frame, the motion-compensated macro block data of I picture of a frame which succeeds, in view of time, the macro block data MB (f) of the present frame, the motion-compensated macro block data of P picture of a frame which succeeds, in view of time, the macro block data MB (f) of the present frame, interpolated macro block data generated from an I picture of a frame precedent, in view of time, to the macro block data MB (f) of the present frame and a P picture succeeding, in view of time, the macro block data MB (f), and interpolated macro block data generated from a P picture of a frame precedent, in view of time, to the macro block data MB (f) of the present frame and a P picture succeeding, in view of time, the macro block data MB (f).
As understood from the above description, the P picture includes the data coded by using the image data of other than the present frame, i.e., interframe-coded data. The B picture is formed only of interframe-coded data so that the B picture cannot be decoded independently. As known, a plurality of related pictures are handled as one group of pictures (GOP) and the pictures are processed by GOP unit.
In general, the GOP is formed of one or a plurality of I pictures and one or a plurality of non-I pictures. In order to facilitate the following description, it is assumed that intraframe-coded image data and bidirectionally predictive-coded image data are the I picture and the B picture, respectively, and one GOP is formed of one B picture and one I picture. However, it is assumed that the B picture processed initially after the processing is started and the B picture processed last before the processing is ended are image data predictive-coded in one direction.
As understood from the above description, in FIG. 2, the I picture is generated at a stage of the output terminal of the frame memory 52, the switch 60, the DCT circuit 64 and the circuits succeeding the DCT circuit 64. In FIG. 2, the B picture is generated at a stage of the output terminal of the frame memory 54, the motion compensation circuit 57, the adder circuit 58, the adder circuit 59, the switch 60, the DCT circuit 64 and the circuits succeeding the DCT circuit 64.
The DCT circuit 64 converts the DC output from the switch 60 into coefficient data of a higher AC component. The quantizing circuit 65 quantizes the coefficient data from the DCT circuit 64 by a predetermined quantization step size. The variable-length coding circuit 60 codes the coefficient data from the quantizing circuit 65 and the motion vector data from the motion detection circuit 51 by some suitable methods such as Huffman coding, run-length coding or the like. The output coding circuit 68 adds the output from the variable-length coding circuit 66 and decoding information EDa supplied through an input terminal 68I with the inner parity and the outer parity, respectively, converts the same into data series of product codes, adds the data series with the synchronization signal or the like, and output the data series through the output terminal 69. In the data in one GOP when data is output, the decoding information, frame data of the B picture, decoding information and frame data of the I picture are successively arranged.
The decoding data EDa is formed of GOP head data indicating a head of the GOP and an inter/intra selection signal SEL. When the GOP head data has a value of "1", the GOP head data indicates that frame data added with the GOP data at the head position are head frame data of the GOP. When the GOP head data has a value of "0", the GOP head data indicates that frame data added with the GOP data at the head position are not head frame data of the GOP but frame data located at the head of the picture.
Though not shown, after the output coding circuit 68 adds the audio data from the audio encoder 12a with the inner parity and the outer parity and converts the same into the data series of product codes as shown in FIG. 1, the output coding circuit 68 subjects the data series to channel coding and outputs the same through the output terminal 69.
An operation of the video encoder 12v will be described. The B picture coded and generated when an encoding processing is started and the B picture coded and generated immediately before the encoding processing is ended will now be described.
When the B picture forming one GOP is generated, the movable contact c of the switch 60 is connected to the inter-side fixed contact a under the control of the inter/intra determining circuit 61.
The motion detection circuit 51 successively carries out motion detection by using the macro block data MB (f) of the present frame and the macro block data MB (f+1) of the frame image data of the succeeding frame. As a result of the motion detection, there are selected macro block data MB (f+1) most similar to the contents of the macro block data MB (f) of the present frame, and there are obtained the motion vector data MV which start from the position of the macro block data MB (f) of the present frame and represent a position of the macro block data MB (f+1). Similarly, the motion detection circuit 51 successively carries out the motion detection by using the macro block data MB (f) of the present frame and the macro block data MB (f-1) of the frame image data of the preceding frame. As a result of the motion detection, there are selected macro block data MB (f-1) most similar to the contents of the macro block data MB (f) of the present frame, and there are obtained the motion vector data MV which start from the position of the macro block data MB (f) of the present frame and represent a position of the macro block data MB (f-1).
The two motion vector data MV are supplied to the variable-length coding circuit 66 and also supplied to the motion compensation circuits 56, 57. The motion compensation circuits extract the macro block data MB (f+1) indicating the motion vector data MV from the frame image data of the succeeding frame. The extracted macro block data MB (f+1) are supplied to the adder circuit 58. On the other hand, the motion compensation circuit 57 extracts the macro block data MB (f-1) indicating the motion vector data MV from the frame image data of the preceding frame. The extracted macro block data MB (f-1) are supplied to the adder circuit 58.
The adder circuit 58 adds the macro block data MB (f+1) from the motion compensation circuit 56 and the macro block data MB (f-1) from the motion compensation circuit 57 and multiples the addition result by a coefficient "1/2" to thereby calculate a mean value of the two macro block data. The added and averaged output is supplied to the adder circuit 59. The adder circuit 59 is supplied with the macro block data MB (f) of the present frame read out from the frame memory 52. Therefore, the adder circuit 59 subtracts the added and averaged output from the adder circuit 58 from the macro block MB (f) of the present frame. The output from the adder circuit 59 is subjected to interframe coding by the DCT circuit 64, the quantizing circuit 65 and the variable-length coding circuit 66, subjected to output coding processing by the output coding circuit 68 and then output therefrom as the B picture.
After all the macro block data MB (f) stored in the frame memory 52 are subjected to the above-mentioned processings, i.e., after the interframe coding processing is finished, the frame image data stored in the frame memory 52 are read out, supplied to the frame memory 54, and stored as image data of the preceding frame in the frame memory 54. On the other hand, subsequent frame image data are stored in the frame memory 52 as the frame image memory of the present frame.
When the I picture forming the one GOP is generated, the movable switch c of the switch 60 is connected to the intra-side fixed contact b under the control of the inter/intra determining circuit 61.
Subsequently, the video decoder 20v shown in FIG. 1 will be described with reference to FIG. 3. FIG. 3 is a structural diagram showing an arrangement inside the video decode shown in FIG. 1.
The video decoder 20v shown in FIG. 3 has an input decoding circuit 71, a variable-length decoding circuit 73, an inverse quantizing circuit 74, an inverse discrete cosine transform (IDCT) circuit 75, a frame memory 76, a frame memory 79, a motion compensation circuit 80, a motion compensation circuit 81, an adder circuit 82, an adder circuit 81, and a switch 84. The input decoding circuit 71 decodes reproduced video and audio data pav supplied thereto from the switching circuit 13 shown in FIG. 1 by channel coding processing, subjects the reproduced video and audio data pav to error correction processing by using the inner and outer parities, supplies the error-corrected video data to the variable-length decoding circuit 73, supplies error-corrected decoding information DDa through an output terminal 720 to the system controller 23 shown in FIG. 1, and supplies the error-corrected audio data to the audio decoder shown in FIG. 1. The variable-length decoding circuit 73 decodes image data of the output from the input decoding circuit 71 to restore the image data to quantized coefficient data and decodes the motion vector data MV to supply the decoded motion vector data MV to the motion compensation circuits 80, 81. The inverse quantizing circuit 74 inverse-quantizes an output from the variable-length decoding circuit 73 to restore the same to the coefficient data subjected to the DCT. The IDCT circuit 75 subjects an output from the inverse quantizing circuit 74 to inverse discrete cosine transform to obtain image data as the I or B picture. The frame memory 76 stores an output from the IDCT circuit 75 in accordance with the read/write control signal supplied from the system controller 23 shown in FIG. 1 through an input terminal 77I. The frame memory 79 stores image data read out from the frame memory 76 in accordance with the read/write control signal supplied from the system controller 23 shown in FIG. 1 through an input terminal 78I. The motion compensation circuit 80 extracts macro block data indicated by the motion vector data MV supplied from the variable-length coding circuit 73 from frame image data stored in the frame memory 79. The motion compensation circuit 81 extracts macro block data indicated by the motion vector data MV supplied from the variable-length coding circuit 73 from frame image data as the I picture from the IDCT circuit 75. The adder circuit 82 adds macro block data from the motion compensation circuit 80 and macro block data from the motion compensation circuit 81 and multiplies the added result by a coefficient "1/2" by a 1/2 multiplier provided therein to thereby obtain an average of addition of the two macro block data. The adder circuit 83 adds an added and averaged output from the adder circuit 82 and difference data as the B picture read out from the frame memory 76 to obtain original macro block data. The switch 84 switch macro block data from the adder circuit 83 and macro block data read out from the frame memory 76 based on the inter/intra selection signal SEL supplied from the system controller 23 shown in FIG. 1 through an input terminal 85I, and supplies the switched output to the reproduction signal-processing circuit 22.
In FIG. 3, the I picture is decoded at a stage from an output terminal of the frame memory 76 to the switch 84. The B picture is decoded in stages from the IDCT circuit 75 through the motion compensation circuit 80 to the adder circuit 82 and from the output terminal of the frame memory 79 through the compensation circuit 81, the adder circuit 82, the adder circuit 83 to the switch 84.
An operation of the video decoder 20v will be described. In order to facilitate the following description, it is assumed that when the image data are decoded, the frame memory 79 holds image data as a decoded I picture of the immediately preceding GOP, the frame memory 76 holds image data as a B picture of a GOP to be decoded, and the IDCT circuit 75 outputs image data as a decoded I picture of the GOP to be decoded. Frame image data as the decoded I picture of the immediately preceding GOP are frame image data of a preceding frame. Frame image data as the B picture of the GOP to be decoded are differential image data of the present frame. Frame image data as decoded I picture of the GOP to be decoded are frame image data of the succeeding frame.
The input decoding circuit 71 subjects the reproduced video and audio data pav from the switching circuit 13 shown in FIG. 1 to the channel coding processing to decode the reproduced video and audio data pav. The decoded reproduced video and audio data pav are error-corrected by the input decoding circuit 71 by using the inner and outer parities. The error-corrected audio data pa are supplied to the audio decoder 21a {shown in FIG. 1. The error-corrected video data pv are supplied to the variable-length decoding circuit 73 shown in FIG. 3. The video data are decoded by the variable-length decoding circuit 73 and converted into quantized coefficient data. The decoded video data are supplied to the inverse quantizing circuit 74 which restores the decoded video data to the coefficient data subjected to the DCT. The video data restored to the coefficient data subjected to the DCT are supplied to the IDCT circuit 75 and restored thereby to original image data. The "original image data" are "difference data" when the image data are the B picture generated by the interframe coding and are "macro block data" when the image data are the I picture generated by intraframe coding.
On the other hand, the input decoding circuit 71 supplies decoding information DDa through an output terminal 720 to the system controller 23 shown in FIG. 1. The system controller 23 shown in FIG. 1 extracts GP head data and the inter/intra selection signal SEL from the decoding information DDa and supplies the inter/intra selection signal SEL as a switching control signal to the switch 84 through the input terminal 85I. Thus, a movable contact c of the switch 84 is connected to an inter-side fixed contact a thereof, because data initially transferred are the B picture. Information indicating a switching timing of the switch 84 based on the inter/intra selection signal SEL is the GOP head data detected from the decoding information DDa. Since the GOP head data is added with every GOP, it is possible to discriminate that one GOP data is data between the detected GOP head data and next detected GOP data.
The motion compensation circuit 80 extracts the macro block data MB (f+1) indicated by the motion vector data MV supplied from the variable-length decoding circuit 73 from frame image data of the succeeding frame as the decoded I picture from the IDCT circuit 75. The macro block data MB (f+1) extracted from the frame image data as the succeeding frame by the motion compensation circuit 80 are supplied to the adder circuit 82.
On the other hand, after the frame image data the decoded I picture of the immediately preceding GOP are stored in the frame memory 79, the motion compensation circuit 81 starts its processing in response to a processing start timing of the motion compensation circuit 80. Specifically, the motion compensation circuit 81 extracts the macro block data MB (f-1) indicated by the motion vector data MV supplied from the variable-length decoding circuit 73 from the frame image data as the decoded I picture of the immediately preceding GOP stored in the frame memory 79. The macro block data MB (f-1) extracted from the frame image data as the preceding frame by the motion compensation circuit 81 are supplied to the adder circuit 82.
While a signal line connected to the output terminal of the variable-length decoding circuit 73 is indicated by a single line a single reference symbol depicting the motion vector is used, the motion vector data of all macro blocks of one frame image data are calculated in every motion detection carried out when image data are encoded. Accordingly, the motion vector data MV supplied to the motion compensation circuit 80 and the motion vector data MV supplied to the motion compensation circuit 81 are different data obtained when image data are encoded.
The macro block data MB (f+1) from the motion compensation circuit 80 and the macro block data MB (f-1) from the motion compensation circuit 81 are added by the adder circuit 82. The addition result is multiplied by a coefficient "1/2" by the 1/2 multiplier of the adder circuit 82 and averaged by the adder circuit 82. An added and averaged output from the adder circuit 82 is supplied to the adder circuit 83.
The adder circuit 83 adds the difference data read out from the frame memory 76 and the added and averaged output from the adder circuit 82. The addition result is supplied as decoded reproduced video data PV of the present frame through the output terminal 86 to the reproduction signal-processing circuit 22 shown FIG. 1.
When the frame memories 76 and 79 are respectively supplied with the read/write control signal R/W from the system controller 23 shown in FIG. 1 through input terminals 77I, 78I, the macro block data of the succeeding frame as the I picture output from the IDCT circuit 75 are supplied to the motion compensation circuit 80 and also supplied to the frame memory 76 and stored thereby.
Significance of the processings in the adder circuit 82 and the adder circuit 83 will be described for confirmation. The adder circuit 58 shown in FIG. 2 calculates the average of the addition of the macro block data MB (f+1) of the succeeding frame obtained by motion compensation of the motion compensation circuit 56 and the macro block data MB (f-1) of the preceding frame obtained by motion compensation of the motion compensation circuit 57. The adder circuit 59 subtracts the added and averaged output from the adder circuit 58. The processing in the adder circuit 59 is shown in the following equation 1: EQU MBd(f)=MB(f)-{MB(f+1)+MB(f-1)}/2! (equation 1)
where MBd (f) is difference data of each of the macro block unit of the present frame.
Accordingly, in order to obtain the macro block data MB (f) of the present frame from the difference data MBd at the video decoder 20v side, calculation of the following equation 2 must be carried out: EQU MB(f)=MBd(f)+{MB(f+1)+MB(f-1)}/2! (equation 2)
where MB (f) and MBd (f) are macro block data of the present frame and difference data of each of the macro block unit of the present frame, respectively.
A symbol "+" at the head of equation 2, i.e., addition corresponds to addition carried out by the adder circuit 83 shown in FIG. 3. A symbol "+" indicating addition of the macro block data MB (f+1 and the macro block data MB (f-1) in braces in equation 2 corresponds to addition carried out by the adder circuit 82 shown in FIG. 3. A value "1/2" used to multiple data in parentheses corresponds to multiplication of the coefficient "1/2".
Accordingly, in order to calculate equation 2, it is necessary to extract the macro block data MB (f+1) from the frame image data of the transferred succeeding frame and to extract the macro block data MB (f-1) from the frame image data of the transferred preceding frame. The motion vector data MV supplied from the variable-length decoding circuit 73 to the motion compensation circuits 80 and 81 are used to carry out the above-mentioned "extraction".
When the above-mentioned processings are repeated to restore all the frame image data of the present frame as the B picture, the system controller 23 shown in FIG. 1 supplies the inter/intra selection signal SEL through the input terminal 85I to the switch 84. In response to the inter/intra selection signal SEL, the movable contact c of the switch 84 is connected to the intra-side fixed contact b. Since the contents of the frame memory 76 is successively changed to the macro block data MB (f+1) of the succeeding frame as the I picture at every processing, the frame image data of the succeeding frame as the I picture are stored in the frame memory 76 at this time.
The frame memory 76 is supplied with the read/write control signal R/W from the system controller 23 shown in FIG. 1 through the input terminal 77I, whereby the frame image data of the succeeding frame as the I picture stored in the frame memory 76 are supplied as the decoded reproduced video data PV through the switch 84 and the output terminal 86 to the reproduction signal-processing circuit 22.
Subsequently, the system controller 23 shown in FIG. 1 will be described with reference to FIG. 4. FIG. 4 is a structural diagram of an inner arrangement of the system controller 23 shown in FIG. 1.
The system controller 23 shown in FIG. 4 has a central processing unit (CPU) 90, a clock generating circuit 94 connected thereto, a bus 91 formed of address, data and control buses connected to the CPU 90, a ROM 92 for storing program data and parameter data, a RAM 93 used to execute processing based on the program data stored in ROM 92 and used as a holding means for temporarily holding the parameter data stored therein, and an input/output port 97 for transmitting and receiving data to and from the respective units shown in FIG. 1. The bus 91 is connected with the ROM 92, the RAM 93 and the input/output port 97.
The clock generating circuit 94 generates a clock signal based on the reference signal REF supplied from the reference signal generator 37 shown in FIG. 1 through an input terminal 95, supplying the clock signal as a system clock to the CPU 90.
A number of terminals connected to the input/output port 97 will be described. These terminals are marked with a reference symbol "I" or "O". If a terminal is marked with reference numeral including the reference symbol "I", it is an input terminal. If a terminal is marked with reference numeral including the reference symbol "O", it is an output terminal. The terminals in FIG. 4 are marked with the same reference numerals in order to facilitate understanding of connection thereof with the respective terminal shown in FIGS. 1, 2 and 3. The system controller 23 will hereinafter be described with reference to FIGS. 1, 2, 3 and 4.
The output terminals 53O and 55O are used to output the read/write control signal R/W and respectively connected to the input terminal 53I, 55I of the frame memory 52, 54 of the video encoder 12v shown in FIG. 2.
The output terminal 62O is used to output a frame pulse Fp and connected to the input terminal 62I of the inter/intra determining circuit 61 of the video encoder 12v shown in FIG. 2.
The input terminal 63I is used to input the frame pulse Fp and connected to the input terminal 630 of the inter/intra determining circuit 61 of the video encoder 12v shown on FIG. 2.
The output terminal 68O is used to output the decoding information EDa and connected to the input terminal 68I of the output coding circuit 68 of the video encoder 12v shown in FIG. 2.
The input terminal 72I is used to input the decoding information DDa and connected to the output terminal 72O of the input decoding circuit 71 of the video decoder 20v shown in FIG. 3.
The output terminals 77O, 78O are used to output the read/write control signal R/W and respectively connected to the input terminals 77I, 78I of the frame memories 76, 79 of the video decoder 20v shown in FIG. 3.
The output terminal 85O is used to output the inter/intra selection signal SEL and connected to the input terminal of the switch 84 of the video decoder 20v shown in FIG. 3.
An output terminal 98 is used to output the control signal CON used for control of the reproduction-side VCR 1 and connected to a control signal input terminal of the system controller 8 of the reproduction-side VCR 1 shown in FIG. 1.
An input terminal 99 is used to input the reproduction time code PLTC from the reproduction-side VCR 1 shown in FIG. 1 and connected to a time code output terminal of the reproduction signal-processing circuit 7 of the reproduction-side VCR 1 shown in FIG. 1.
An output terminal 100 is used to output the control signal for control of the recording signal-processing circuit 11 of the recording-side VCR 10 and connected to a control signal input terminal of the recording signal-processing circuit 11 of the recording-side VCR 10 shown in FIG. 1.
An output terminal 101 is used to output the control signal for control of the reproduction signal-processing circuit 22 of the recording-side VCR 10 and connected to a control signal input terminal of the reproduction signal-processing circuit 22 of the recording-side VCR 10 shown in FIG. 1.
An input/output terminal 102 is used to output the time code data PLTC generated by the system controller 23 and to input the reproduction time code LTC supplied from the switching circuit 13 of the recording-side VCR 10 shown in FIG. 1. The input terminal 102 is connected to input and output terminals of the switching circuit 13 of the recording-side VCR 10 shown in FIG. 1.
An input/output terminal 103 is used to input a drum switching pulse SWP supplied from the tape transport unit 14 shown in FIG. 1 through the servo control circuit 24 and to output various control signals by which the servo control circuit 24 shown in FIG. 1 controls a drum motor and a capstan motor of the rotary drum of the tape transport unit 14 and the tape transport unit 14 carries out loading and unloading of the magnetic tape 17, ejection of the video tape cassette and so on. The input/output terminal 103 is connected to the input/output terminal of the servo control circuit 24 shown in FIG. 1.
An input/output terminal 104 is used to input data KEY indicating contents of operation from the console panel 25 shown in FIG. 1 and to output the image data indicating the contents of the time code data displayed on the LCD 36. The input/output terminal 104 is the input/output terminal of the console panel 25 shown in FIG. 1.
Subsequently, there will be described functions which the system controller 23 has after power is supplied to the system controller.
When the power is supplied from a power supply to the system controller 23, the program data and the parameter data stored in the ROM 92 become resident in a main memory of the CPU 90, whereby the CPU 90 has a number of functions shown in a large block shown by a one-dot chain line in FIG. 4.
A tape transport unit controlling means 105 supplies a control signal through an input/output port 97, an input/output terminal 103 and the servo control circuit 24 shown in FIG. 1 to the tape transport unit 14, thereby controlling the tape transport unit 14 to carry out some operations such as to load and unload the magnetic tape 17 thereonto and therefrom, to eject the video tape cassette therefrom, or the like. The tape transport unit controlling means 105 generates a recording track signal RT based on the drum switching pulse SWP supplied from the tape transport unit 14 shown in FIG. 1 through the input terminal 103.
When data is recorded, a high "1" level of the recording track signal RT corresponds to "recording" and a low "0" level thereof corresponds to "non-recording". When data is reproduced, the recording track signal RT becomes the same signal as the drum switching pulse SWP.
A servo control means 106 supplies a control signal through the input/output port 97 and the input terminal 103 to the servo control circuit FIG. 1, thereby controlling the servo control circuit 24 to effect servo control on the drum motor (not shown) of the tape transport unit 14 and the capstan motor (not shown) thereof.
An LCD control means 107 generates image data indicating contents of the time code LTC supplied from the reproduction-side VCR 1 shown in FIG. 1 through the input terminal 99 and supplies the image data through the input/output port 97 and the input/output terminal 104 to the LCD 36 shown in FIG. 1, thereby controlling the LCD 36 to display the contents of the time code LTC as an image and controlling the LCD 36 to be driven.
An external VCR controlling means 108 supplies control commands of some operations, such as reproduction, recording, fast forwarding, rewinding, stop, pause or the like, the control signal CON including the time code data LTC through the input/output port 97 and the input/output terminal 98 to the system controller 8 of the reproduction-side VCR 1 shown in FIG. 1, thereby controlling the reproduction-side VCR 1 shown in FIG. 1 to carry out the above operations.
Though an input terminal and an output terminal are not shown in FIG. 4 in order to facilitate the description, the timing controlling means 109 supplies various timing signal used as reference to the respective units shown in FIG. 1. The timing controlling means 109 supplies the frame pulse Fp through the input/output port 97 and the output terminal 620 to the inter/intra determining circuit 61 of the video encoder 12v.
A time code generating means 110 generates the time code LTC for the recording-side VCR 10 and supplies the generated time code LTC through the input/output port 97, the input/output terminal 102 and the switching circuit 13 shown in FIG. 1 to the recording and reproducing head 16.
A key input discriminating means 111 discriminates which command is made through the console panel 25 shown in FIG. 1, on the basis of the input data KEY supplied from the console panel 25 through the input/output terminal 104 and the input/output port 97.
An external memory controlling means 112 supplies the read/write control signal R/W through the input/output port 97 and the output terminal 53O, 55O, 77O or 78O to the frame memories 52, 54 shown in FIG. 2 and the frame memories 76, 79 shown in FIG. 3, thereby controlling data to be read from and written in the frame memories 52, 54, 76 and 79.
An inside memory controlling means 113 supplies the read/write control signal to the ROM 92 and the RAM 93 shown in FIG. 4, thereby controlling operations of reading out the data stored in the ROM 92 and the RAM 93 and writing data in the RAM 93.
A decoding information generating means 114 supplies the inter/intra selection signal SEL supplied from the inter/intra determining circuit 61 of the video encoder 12v shown in FIG. 2 through the input terminal 63I and the input/output port 97 and the decoding information of the GOP head data from a GOP discriminating means 116, through the input/output port 97 and the output terminal 68O to the output coding circuit 68 of the video encoder 12v shown in FIG. 2.
A decoding information extracting means 115 extracts the inter/intra selection signal SEL and the GOP head data described above from the decoding information supplied from the input decoding circuit 71 of the video decoder 20v shown in FIG. 3 through the input terminal 72I and the input/output port 97.
The GOP discriminating means 116 generates the GOP head data based on the inter/intra selection signal SEL supplied from the inter/intra determining circuit 61 of the video encoder shown in FIG. 2 through the input terminal 63I and the input/output port 97 and the frame pulse Fp generated by the timing controlling means 109, supplying the generated GOP head data to the decoding information generating means 114. In the decoding processing, the GOP discriminating means 116 discriminates the head of the GOP based on the GOP head data extracted by the decoding information extracting means 115, supplying the discriminated results to an inter/intra discriminating means 117.
In the decoding processings, the inter/intra discriminating means 117 discriminates whether coding is the interframe coding of intraframe coding based on the inter/intra selection signal SEL extracted by the decoding information extracting means and discriminated results from the GOP discriminating circuit 116, supplying the inter/intra selection signal SEL through the input/output port 97 and the output terminal 85O to the switch 84 of the video decoder 20v shown in FIG. 3.
A time code reading means 118 reads the reproduced time code PLTC supplied from the reproduction-side VCR 1 shown in FIG. 1 through the input terminal 99 and the input/output port 97 and the reproduced time code LTC reproduced by the recording and reproducing head 16 of the recording-side VCR 10 and supplied therefrom through the input/output terminal 102 and the input/output port 97.
A time code comparing means 119 carries out at least two comparing operations. The first comparing operation is carried out to detect whether or not the reproduction time code PLTC supplied from the reproduction-side VCR 1 obtained when recording or reproduction is carried out is coincident with the time code stored in the RAM 93.
In order to synchronize the reproduction-side VCR 1 and the recording-side VCR 10 in their pre-roll period so that difference between time codes at the reproduction starting points thereof should constantly be a predetermined difference, the other comparing operation is carried out to detect whether or not a desired difference and an actual difference are equal to each other. When video data recorded on a portion from an optional first position to an optional second position of the magnetic tape 3 are recorded on a portion succeeding an optional recording position of the magnetic tape 17 of the video tape cassette loaded into the recording-side VCR 10, the desired difference is difference between a time code recorded at an optional first position on the magnetic tape 3 of the video tape cassette loaded into the reproduction-side VCR 1 and a time code recorded at the optional position on the magnetic tape 17 of the video tape cassette loaded into the recording-side VCR 10. If the reproduction-side VCR 1 and the recording-side VCR 10 are synchronized so that the desired difference and the actual difference should be constant, then it is possible to record a desired recording signal on the magnetic tape 3 on a portion succeeding the desired position of the magnetic tape 17.
Subsequently, a control operation of the system controller 23 shown in FIG. 4 will be described with reference to flowcharts shown in FIGS. 5 to 11. Means for mainly carrying out control operations are the above-mentioned means of the CPU 90. The terminals and the input/output port 97 have already been described and therefore need not to be described in the following description in order to avoid long sentences which prevents contents of the control operations of the respective means for mainly carrying out the control operations from being understood.
In step S1 shown in FIG. 5, the key input discriminating means 111 determines whether or not a "0" key of the ten key pad 34 of the console panel 25 shown in FIG. 1 is pressed. If it is determined as "YES" in step S1, then the process proceeds to step S150. If it is determined as "NO", then the process proceeds to step S2. An expression of "to press the "0" key of the ten-key pad 34" is described in order to facilitate the description.
In step S150, the CPU 90 shown in FIG. 4 carries out a processing based on a reproduction-side setting processing routine. The process proceeds to step S200. The reproduction-side setting processing is a processing for setting which portion of image data recorded on the magnetic tape 3 of the video tape cassette loaded into the reproduction-side VCR 1 shown in FIG. 1. Specifically, in the processing, data input when the a key of the ten-key pad 34 of the console panel 25 shown in FIG. 1 is pressed are held as time code data by pressing the enter key 34.
In step S200, the CPU 90 shown in FIG. 4 carries out a recording-side setting processing routine. The process proceeds to step S250. The recording-side setting processing is a processing for setting from which position on the magnetic tape 17 of the video tape cassette loaded into the recording-side VCR 10 shown in FIG. 1 the recording is started.
In step S250, the CPU 90 shown in FIG. 4 carries out a processing based on an insert edition processing routine. The process is ended. The insert edition processing is a processing for recording an insert image determined in step S150 on a portion succeeding the recording position, determined in step S250, of the magnetic tape 17 of the video tape cassette loaded into the recording-side VCR 10.
In step S2, the key input discriminating means 111 shown in FIG. 4 discriminates whether or not the reproduction key 27 of the console panel 25 shown in FIG. 1 is pressed. If it is determined as "YES" in step S2, then the process proceeds to step S100. If it is determined as "NO" in step S100, then the process proceeds to step S1000.
In step S100, the CPU 90 shown in FIG. 4 carries out a processing based on a reproduction processing routine. The process is ended. In step S100, the reproduction processing is a processing for reproducing operation.
In step S1000, the CPU 90 shown in FIG. 4 carries out a processing based on other processing routine. The process is ended. The "other processing routine" means processings such as a recording processing, but in this embodiment, the "other processing routine" need not be described. Therefore, it is only suggested that the "other processing routine" is provided and its contents will not be described.
FIGS. 6, 7 are flowcharts used to explain the control operation based on the reproduction side setting processing routine in step S150 of the flowchart shown in FIG. 5.
In step S151, the key input discriminating means 111 shown in FIG. 4 determines whether or not a key is pressed. If it is determined as "YES" in step S151, then the process proceeds to step S152.
In step S152, the key input discriminating means 111 determines whether or not the enter key 35 of the console panel 25 shown in FIG. 1 is pressed, based on the contents of the input data KEY. If it is determined as "YES" in step S153, then the process proceeds to step S153. If it is determined as "NO" therein, then the process proceeds to step S154.
In step S153, in accordance with a command from the key input discriminating means 111 shown in FIG. 4, the inside memory control means 113 controls the data held by the RAM 93 to be stored again in the RAM 93 as time code data Pin at an in-point. Then, the process proceeds to step S155.
In step S154, in accordance with the command from the key input discriminating means 111 shown in FIG. 4, the inside memory controlling means 113 controls the input data KEY to be temporarily held in the RAM 93. The process proceeds to step S151 again.
Processings in steps S151 to S154 will be described. In the reproduction-side setting processing routine, an in-point and an out-point on the magnetic tape 3 of the video tape cassette loaded into the reproduction-side VCR 1 are set by pressing the ten-key pad 34 and the enter key 35 of the console panel 25 shown in FIG. 1. As long as the key input discriminating means 111 shown in FIG. 4 does not determine that the enter key 35 is pressed, the input data KEY supplied by pressing the ten-key pad 34 are temporarily stored in the RAM under the control of the inside memory controlling means 112 in step S154. If in step S152 the key input discriminating means 111 determines that the enter key 35 is pressed, then in step S153 the data series of the input data KEY temporarily held in the RAM 93 at the time of determination are determined as one previous time code data Pin.
If contents of the time code data the user inputs are "01h (hour) 01m (minute) 01s (second) 01 (frame)", then the user should input "01010101" by using the ten-key pad 34 shown in FIG. 1. If the user presses the enter key 35 after the user inputs the time code by using the ten-key pad 34, then the input data "01010101" are stored in the RAM 93 as the time code data.
In step S155, the key input discriminating means 111 shown FIG. 4 determines whether or not the key is pressed. If it is determined as "YES" in step S155, then the process proceeds to step S156.
In step S156, the key input discriminating means 111 shown in FIG. 4 determines whether or not the enter key 35 is pressed based on the contents of the input data KEY. If it is determined as "YES", then the process proceeds to step S157. If it is determined as "NO", the process proceeds to step S158.
In step S157, in accordance with the command from the key input discriminating means 111 shown in FIG. 4, the inside memory controlling means 113 controls the data held in the RAM 93 to be stored again in the RAM 93 as time code data Pout of the out-point. Then, the process proceeds to step S159 of the flowchart shown in FIG. 7.
In step S158, in accordance with the command from the key input discriminating means 111 shown in FIG. 4, the inside memory controlling means 113 controls the input data KEY to be held in the RAM 93 temporarily. Then, the process proceeds to step S156 again.
The above-mentioned processings in steps S155 to S158 are steps for inputting the time code of the out-point. In the processings in steps S155 to S158, the time code of the output-point is determined in the similar process to steps S151 to S154.
In step S159, the external VCR controlling means 108 shown in FIG. 4 supplies the control signal CON commanding reproduction to the system controller 8 of the reproduction-side VCR 1 shown in FIG. 1. Based on the control signal CON, the system controller 8 of the reproduction-side VCR 1 controls the tape transport unit 2 and the servo control circuit 6 to start the reproducing operation of the tape transport unit 2. When the reproducing operation of the reproduction-side VCR 1 is started, the reproduced time code data PLTC are supplied from the reproduction-side VCR 1 to the system controller 23 of the recording-side VCR 10. The time code reading means 118 shown in FIG. 4 read the reproduction time code data PLTC supplied from the reproduction-side VCR 1 and supplies the read reproduction time code data PLTC to the RAM 93. The inside memory controlling means 112 supplies the read/write control signal to the RAM 93 under the control of the time code reading means 118. Based on the read/write control signal, the reproduction time code data PLTC are stored in the RAM 93. Then, the process proceeds to step S160.
In step S160, the external VCR controlling means 108 shown in FIG. 4 supplies the control signal CON commanding stop to the system controller 8 of the reproduction-side VCR 1 shown in FIG. 1. Based on the control signal CON, the system controller 8 of the reproduction-side VCR 1 controls the tape transport 2 and the servo control unit 6 to stop the reproducing operation of the tape transport unit 2. Then, the process proceeds to step S161.
In step S161, the inside memory controlling means 113 read the reproduction time code data PLTC and the time code data Pin of the in-point from the RAM 93 under the control of the time code comparing means. The read reproduction time code data PLTC and the read time code data Pin of the in-point are supplied to the time code comparing means 119. The time code comparing means 119 compares the reproduction time code data PLTC and the time code data Pin of the in-point. Then, the process proceeds to step S162.
In step S162, the time code comparing means 119 shown in FIG. 4 determines whether or not a position on time base of the reproduction time code data PLTC are prior to a position on time base of the time code data Pin of the in-point. If it is determined as "YES", then the process proceeds to step S163. If it is determined as "NO", then the process proceeds to step S167. The determination in step S162 is carried out to determine whether the reproduction-side VCR 1 carries out a rewinding operation or fast forwarding operation in order to set a position of the magnetic tape to the position indicated by the time code data Pin of the in-point.
In step S163, the external VCR controlling means 108 shown in FIG. 4 supplies the control signal CON commanding rewinding to the system controller 8 of the reproduction-side VCR 1 shown in FIG. 1. Based on the control signal, the system controller 8 of the reproduction-side VCR 1 controls the tape transport unit 2 and the servo control unit 6 to start a rewinding operation of the tape transport unit 2. Then, the process proceeds to step S164.
In step S164, the time code reading means 118 shown in FIG. 4 reads the reproduction time code PLTC supplied from the reproduction-side VCR 1 and supplies the read reproduction time code data PLTC to the RAM 93. The inside memory controlling means 113 supplies the read/write control signal to the RAM 93 under the control of the time code reading means 118. Based on the read/write control signal, the reproduction time code data PLTC are stored in the RAM 93. Then, the process proceeds to step S165.
In step S165, under the control of the time code comparing means 119 shown in FIG. 4, the inside memory control means 113 reads the reproduction time code data PLTC and the time code data Pin of the in-point from the RAM 93. The read reproduction time code data PLTC and the read time code data Pin of the in-point are supplied to the time code comparing means 119. The time code comparing means 119 compares the reproduction time code data PLTC and the time code data Pin of the in-point and determines whether or not the position on time base of the reproduction time code data PLTC are several-second previous to the position on time base of the time code data Pin of the in-point. If it is determined as "YES", the process proceeds to step S166.
In step S166, the external VCR controlling means 108 supplies the control signal CON commanding pause to the system controller 8 of the reproduction-side VCR 1 shown in FIG. 4. Based on the control signal, the system controller 8 of the reproduction-side VCR 1 controls the tape transport unit 2 and the servo control unit 6 to stop the rewinding operation of the tape transport unit 2 and thereafter set the tape transport unit 2 in its pause mode. The process proceeds from the reproduction-side setting processing routine to the recording-side setting processing routine in step S200 in the main routine shown in FIG. 5.
In step S162, if it is determined as "NO", then the process proceeds to step S167. In step S167, the external VCR controlling means 108 shown in FIG. 4 supplies the control signal CON commanding fast forwarding to the system controller 8 of the reproduction-side VCR 1 shown in FIG. 1. Based on the control signal, the system controller 8 of the reproduction-side VCR 1 controls the tape transport unit 2 and the servo control unit 6 to start the fast forwarding operation of the tape transport unit 2. Then, the process proceeds to step S164.
FIGS. 8 and 9 are flowcharts used to explain control operations based on the recording-side setting processing routine in step S200 of the flowchart shown in FIG. 5.
In step S201, the key input discriminating means 111 shown in FIG. 4 determines whether or not the key is pressed. If it is determined as "YES", then the process proceeds to step S202.
In step S202, the key input discriminating means 111 shown in FIG. 4 determines whether or not the enter key 35 shown in FIG. 1 is pressed, based on the contents of the input data KEY. If it is determined as "YES", then the process proceeds to step S203. If it is determined as "NO", then the process proceeds to step S204.
In step S203, in accordance with the command from the key input discriminating means 111 shown in FIG. 4, the inside memory controlling means 113 controls the data held by the RAM 93 to be stored in the RAM 93 as the time code data Rin of the in-point (the recording start point) again. Then, the process proceeds to step S205 of the flowchart shown in FIG. 9.
In step S204, in accordance with the command from the key input discriminating means 111 shown in FIG. 4, the inside memory control means 113 temporarily holds the input data KEY in the RAM 93. Then, the process proceeds to step S201.
The above-mentioned processings in steps S201 to S204 are processings for inputting the time code of the recording start point on the magnetic tape 17 of the video tape cassette loaded into the recording-side VCR 10. In the processings in steps S201 to S204, the time code of the in-point is determined in the similar process to that in steps S151 to S154 of the reproduction-side setting processing routine and that in steps S155 to S158 thereof.
In step S205, the tape transport unit controlling unit 105 shown in FIG. 4 supplies the control signal commanding reproduction through the servo control circuit 24 to the tape transport unit 2 to thereby control the tape transport unit 2 to start its reproducing operation. When the reproducing operation of the tape transport unit 14 is started, the tape transport unit 14 supplies the time code data LTC to the system controller 23. The time code reading means 118 shown in FIG. 4 supplies the read time code data LTC to the RAM 93. The inside memory control means 112 supplies the read/write control signal to the RAM 93 under the control of the time code reading means 118. Based on the read/write control signal, the time code data LTC are stored in the RAM 93. Then, the process proceeds to the step S206.
In step S206, the tape transport unit controlling means 105 shown in FIG. 4 supplies the control signal commanding stop through the servo control circuit 24 to the tape transport unit 14 to control the tape transport unit 14 to stop its reproducing operation. Then, the process proceeds to step S207.
In step S207, under the control of the time code comparing means 119 shown in FIG. 4, the inside memory controlling means 113 read the time code data LTC and the time code data Rin from the RAM 93 and supplies the read time code data LTC and the read time code data Rin to the time code comparing means 119. The time code comparing means 119 compares the time code data LTC and the time code data Rin of the in-point. Then, the process proceeds to step S208.
In step S208, the time code comparing means 119 shown in FIG. 4 determines whether or not the position on time base of the time code data LTC is prior to the position on time base of the time code data Rin of the in-point. If it is determined as "YES", then the process proceeds to step S209. If it is determined as "NO", then the process proceeds to step S213. The determination in step S208 is carried out to determine whether the tape transport unit 14 carries out its rewinding operation or fast forwarding operation in order to set the position of the magnetic tape 17 to the position indicated by the time code data Pin of the in-point.
In step S209, the tape transport unit controlling means 105 shown in FIG. 4 supplies the control signal commanding rewinding through the servo control circuit 24 to the tape transport unit 14 to control the tape transport unit 14 to start its rewinding operation. Then, the process proceeds to step S210.
In step S210, the time code reading means 118 shown in FIG. 4 reads the time code data LTC supplied from the tape transport unit 14 and supplies the read reproduction time code data LTC to the RAM 93. The inside memory controlling means 113 supplies the read/write control signal to the RAM 93 under the control of the time code reading means 118. Based on the read/write control signal, the time code data LTC are stored in the RAM 93. Then, the process proceeds to step S211.
In step S211, under the control of the time code comparing means 119 shown in FIG. 4, the inside memory controlling means 113 read the time code data LTC and the time code data Rin of the in-point from the RAM 93. The read time code data LTC and the read time code data Rin of the in-point are supplied to the time code comparing means 119. The time code comparing means 119 compares the time code data LTC and the time code data Rin of the in-point and determines whether or not the position on time base of the time code data LTC is several-second previous to the position on time base of the time code data Rin of the in-point. If it is determined as "YES", the process proceeds to step S212.
In step S212, the external VCR controlling means 108 shown in FIG. 4 supplies the control signal commanding pause through the servo control circuit 24 shown in FIG. 1 to the tape transport unit 14 to control the tape transport unit 2 to stop its rewinding operation and then to set the tape transport unit 2 in its pause state. Then, the process proceeds from the recording-side setting processing routine to the insert edition processing routine in step S250 of the main routine shown in FIG. 5.
In step S213, tape transport unit controlling means 105 shown in FIG. 4 supplies the control signal commanding fast forwarding through the servo control circuit 24 to the tape transport unit 14 to control the tape transport unit 14 to start its fast forwarding operation, Then, the process proceeds to step S210.
FIG. 10 is a flowchart used to explain the control operations based on the insert edition processing routine in step S250 of the flowchart shown in FIG. 5.
In step S251, the external VCR controlling means 108 shown in FIG. 4 supplies the control signal CON commanding reproduction to the system controller 8 of the reproduction-side VTR 1 shown in FIG. 1. Based on the control signal, the system controller 8 of the reproduction-side VTR 1 controls the tape transport unit 2 and the servo control circuit 6 to start the reproducing operation of the tape transport unit 2. When the reproducing operation of the reproduction-side VCR 1 is started, the reproduction-side VCR 1 supplies the reproduction time code data PLTC to the system controller 23. The time code reading means 118 shown in FIG. 4 read the reproduction time code data PLTC supplied from the reproduction-side VCR 1 and supplies the read reproduction time code data PLTC to the RAM 93. The inside memory controlling means 112 supplies the read/write control signal to the RAM 93 under the control of the time code reading means 118. Based on the control signal, the reproduction time code data PLTC are stored in the RAM 93. Then, the process proceeds to step S252.
In step S252, the tape transport unit controlling means 105 shown in FIG. 4 supplies the control signal commanding reproduction through the servo control circuit 24 to the tape transport unit 14 to control the tape transport unit 14 to start its reproducing operation. When the reproducing operation of the tape transport unit 14 is started, the tape transport unit 2 supplies the time code data LTC to the system controller 23. The time code reading means 118 shown in FIG. 4 reads the time code data LTC supplied from the tape transport unit 14 and supplies the read time code data LTC to the RAM 93. The inside memory controlling means 113 supplies the read/write control signal to the RAM 93 under the control of the time code reading means 118. Based on the read/write control signal, the time code data LTC are stored in the RAM 93. Then, the process proceeds to step S253.
In step S253, under the control of the time code comparing means 119, the inside memory control means 113 reads the reproduction time code data PLTC and the time code data LTC. The read reproduction time code data PLTC and the read time code data LTC are supplied to the time code comparing means 119. The time code comparing means 119 calculates difference between the reproduction time code data PLTC from the reproduction-side VCR 1 and the time code data LTC from the tape transport unit 14. The time code comparing means 119 determines whether or not the obtained difference is coincident difference between the time code Pin of the in-point on the magnetic tape 3 of the video tape cassette loaded into the reproduction-side VCR 1 and the time code Rin of the in-point on the magnetic tape 17 of the video tape cassette loaded into the recording-side VCR 10. The time code comparing means 119 supplies the result to the external VCR controlling means 108 and the tape transport unit controlling means 105. Based on the result of comparison, the external VCR controlling means 108 controls the reproduction-side VCR 1 and the tape transport unit controlling means 105 controls the tape transport unit 14, whereby the reproduction-side VCR 1 and the tape transport unit 14 are synchronized with each other.
In step S254, the time code reading means 118 shown in FIG. 4 reads the reproduction time code data PLTC supplied from the reproduction-side VCR 1 and supplies the read reproduction time code data PLTC to the RAM 93. The inside memory controlling means 112 supplies the read/write control signal to the RAM 93 under the control of the time code reading means 118. Based on the read/write control signal, the reproduction time code data PLTC are stored in RAM 93. Then, the process proceeds to step S255.
In step S255, under the control of the time code comparing means 119 shown in FIG. 4, the inside memory control means 113 reads the reproduction time code data PLTC and the time code data Pin of the in-point form the RAM 93. The time code comparing means 119 compares the reproduction time code data PLTC and the time code data Pin of the in-point and determines whether or not the position on time base of the reproduction time code data PLTC is the position on time base of the time code data Pin of the in-point. If it is determined as "YES", then the process proceeds to step S256.
In step S256, the decoding information generating means 114 shown in FIG. 4 supplies the decoding information EDa formed of the GOP head data and the inter/intra selection signal to the output coding circuit 68 of the video encoder 12v shown in FIG. 2. Then, the process proceeds to step S257.
In step S257, the tape transport unit controlling means 105 supplies the control signal commanding recording through the servo control circuit 24 to the tape transport unit 14, thereby controlling the tape transport unit 14 to start its recording operation. When the recording operation of the tape transport unit 14 is started, the output coding circuit 68 of the video encoder 12v shown in FIG. 2 supplies the video data, the audio data and the decoding information for output through the switching circuit 13 shown in FIG. 1 to the recording and reproducing head 15 which records the video data, the audio data and the decoding information on the magnetic tape 17 from the position of the in-point Rin on slant tracks formed thereon. Then, the process proceeds to step S258.
In step S258, the time code reading means 118 shown in FIG. 4 reads the reproduction time code data PLTC supplied from the reproduction-side VCR 1 and supplies the read reproduction time code data PLTC to the RAM 93. The inside memory controlling means 113 supplies the read/write control signal to the RAM 93 under the control of the time code reading means 118. Based on the read/write control signal, the reproduction time code data PLTC are stored in the RAM 93. Then, the process proceeds to step S259.
In step S259, under the control of the time code comparing means 119, the inside memory controlling means 113 reads the reproduction time code data PLTC and the code data Pout of the out-point from the RAM 93. The read reproduction time code data PLTC and the read code data Pout of the out-point are supplied to the time code comparing means 119. The time code comparing means 119 compares the reproduction time code data PLTC and the time code data Pout of the out-point and determines whether or not the position on time base of the reproduction time code data PLTC is the position on time base of the time code data Pout of out-point. If it is determined as "YES", then the process proceeds to step S260.
In step S260, the tape transport unit controlling means 105 supplies the control signal commanding cancellation of recording operation to the tape transport unit 14 through the servo control unit 24, thereby controlling the tape transport unit 14 to cancel its recording operation. Then, the process proceeds to step S261.
In step S261, the tape transport unit controlling means 105 shown in FIG. 4 supplies the control signal commanding stop through the servo control circuit 2 to the tape transport unit 14, thereby controlling the tape transport unit 14 to stop its operation. Then, the process proceeds to step S262.
In step S262, the external VCR controlling means 108 shown in FIG. 4 supplies the control signal CON commanding stop to the system controller 8 of the reproduction-side VCR 1. Based on the control signal, the system controller 8 of the reproduction side VCR 1 controls the tape transport unit 2 and the servo control circuit 6 to thereby stop the reproducing operation of the tape transport unit 2. The process proceeds from the insert edition processing routine and the processings in the main routine shown in FIG. 5 are ended.
FIG. 11 is a flowchart used to explain the control operation based on the reproduction processing routine in step S100 of the flowchart shown in FIG. 5.
In step S101, the tape transport unit controlling means 105 supplies the control signal commanding reproduction through the servo control circuit 24 to the tape transport unit 14 to control the tape transport unit 14 to start its reproducing operation. When the reproducing operation of the tape transport unit 14 is started, the reproduced data from the tape transport unit 14 are supplied to the input decoding circuit 71. The input decoding circuit 71 subjects the video data, the audio data and the decoding information DDa to decoding processing based on the channel decoding and the error correction processing and then supplies the video data to the variable-length coding circuit 73, the audio data to the audio decoder 21a shown in FIG. 1 and the decoding information DDa to the system controller 23. The decoding information extracting means 115 shown in FIG. 4 obtains the decoding information DDa and supplies the decoding information DDa to the RAM 93. The inside memory controlling means 113 supplies the read/write control signal to the RAM 93 under the control of the decoding information extracting means 115. Based on the read/write control signal, the decoding information DDa extracted by the decoding information extracting means 115 are stored in the RAM 93. Then, the process proceeds to step S102.
In step S102, under the GOP discriminating means 116 shown in FIG. 4, the inside memory controlling means 113 supplies the read/write control signal to the RAM 93. Based on the read/write control signal, the GOP head data stored in the RAM 93 are read therefrom. The GOP head data read from the RAM 93 are supplied to the GOP discriminating means 116. The GOP discriminating means 116 discriminates whether or not the GOP head data supplied from the RAM 93 has a value of "1". If it is determined as "YES", then the process proceeds to step S104. If it is determined as "NO", then the process proceeds to step S103.
In step S103, the GOP discriminating means 116 shown in FIG. 4 discriminates whether or not the GOP head data supplied form the RAM 93 has a value of "0". If it is determined as "YES", then the process proceeds to step S104. If it is determined as "NO", then the process proceeds to step S106.
In step S104, under the control of the inter/intra discriminating means 117 shown in FIG. 4, the inside memory controlling means 113 supplies the read/write control signal to the RAM 93. Based on the read/write control signal, the inter/intra selection signal SEL stored in the RAM 93 are read therefrom. The inter/intra selection signal SEL read from the RAM 93 are supplied to the inter/intra determining means 117. Then, the process proceeds to step S105.
In step S105, the inter/intra determining means 117 supplies the inter/intra selection signal SEL read from the RAM 93. Based on the inter/intra selection signal SEL, the movable contact c of the switch 84 is connected to the inter-side fixed contact a or the intra-side fixed contact b to carry out inter/intra switching. Then, the process proceeds to step S106.
In step S106, the external memory controlling means 112 shown in FIG. 4 controls the frame memories 76, 79 shown in FIG. 3 to read and write data from and in the frame memories 76, 79. Then, the motion compensation circuits 80, 81 and the adder circuits 82, 83 start the processings for restoring the original macro block data. Then, the process proceeds to step S107.
In step S107, under the control of the timing controlling means 109 shown in FIG. 4, the variable-length decoding circuit 73 shown in FIG. 3 supplies the motion vector data MV to the motion compensation circuits 80, 81. Then, the process proceeds to step S108.
In step S108, the key input discriminating means 111 shown in FIG. 4 determines whether or not the stop key 29 shown in FIG. 1 is pressed. If it is determined as "YES", the process proceeds from the reproduction processing routine to the main routine shown in FIG. 5 and then is ended.
In the reproduction processing routine, the inter/intra switching is carried out at the GOP head and the picture head and the control on decoding the data is carried out by a macro block unit.
However, the insert edition in the above-mentioned editing system is encountered with a problem which should be solved. This problem will be described with reference to FIG. 12.
FIG. 12 is a diagram used to explain disadvantages caused when the insert edition is carried out in the above-mentioned editing system described with reference to FIGS. 1 through 11.
FIG. 12A shows the in-point Pin and out-point Pout the user sets in the insert image in the reproduction-side setting processing routine in step S150 of the flowchart shown in FIG. 5. FIG. 12B shows the frame numbers of the frame data recorded on the magnetic tape 17 of the video tape cassette loaded into the recording-side VCR 10 shown in FIG. 1. FIG. 12C shows a picture type of the data, corresponding to the frame number shown in FIG. 12B, recorded on the magnetic tape 17. In FIG. 12C, left-side letters of reference symbols depict the frame types and right-side numerals thereof depict the frame numbers. For example, the recorded data of the frame number "0" are marked with reference symbols "B0". The reference symbol "B0" represent a B picture of the frame number "0". For example, reference symbols "I1" represents an I picture of the frame number "1". It is assumed similar to the above description that one GOP is formed of two frames and includes a B picture and an I picture.
Study of FIGS. 12A, 12B and 12C reveals assumption that, as shown in FIG. 12C, time code data recorded on a position where data of fifth frame on the magnetic tape 17 are set as the in-point (recording start point) Rin, an image on the magnetic tape 3 of the video tape cassette from the recording position of the time code data Pin of the in-point to a recording position of the time code data of the out-point Pout are recorded as the insert image on the magnetic tape 17 of the video tape cassette loaded into the recording-side VCR 10 from the position of the in-point Rin thereon.
FIG. 12E is a diagram showing an insertion state by using a level of the control signal. In FIG. 12E, a period when the control signal is at high "1" level is a period in which an image is inserted. Specifically, FIG. 12E shows which data-recorded portion on the magnetic tape 17 of the video tape cassette of the recording-side VCR 10 is to be overwritten by the insert edition. FIG. 12F shows insert images I2', B3', I' and BS' which are reproduced by the reproduction-side VCR 1 and are to be recorded on the magnetic tape 17 of the recording-side VCR 10. As shown in FIG. 12J, an active period of the recording track signal supplied from the tape transport unit controlling means 105 shown in FIG. 4 to the tape transport unit 14 shown in FIG. 1, i.e., a recording period has the same length as the high "1" level period of the insertion period shown in FIG. 12F. Therefore, as shown in FIG. 12J, the insert image shown in FIG. 12F is recorded on the magnetic tape 17 of the recording-side VCR 10 with slant tracks being formed only in the high "1" level period of the recording track signal.
FIG. 12K shows a track pattern on the magnetic tape 17. Study of FIG. 12K reveals that two tracks are formed on the magnetic tape 17 per one GOP, one of them being a recording region for the B picture and the I picture and the other thereof being a region for the I picture. In the GOP at the head position of the insertion region, there are inserted I picture I2' and a B picture B4 and an I picture I5 originally recorded on the magnetic tape 17. In the GOP at the last position of the insertion region, there are inserted B and I pictures B5' and I6' and an originally recorded I picture I9. The I picture I6' is the I picture I6' of the inserted image and is recorded on an upper portion of the track as shown in FIG. 12. FIG. 12L shows the time code data which are recorded on the magnetic tape 17 with longitudinal tracks being formed.
As described above, the I picture is the picture generated by the intraframe coding so that the I picture is restored by the decoding processings carried out at a stage from the input decoding circuit 71 to the IDCT circuit 75. On the other hand, the B picture is the picture generated by the interframe coding so that the B picture must be subjected to the decoding processings and then subjected to restoring processings using the motion compensation circuits 80, 81 and the adder circuits 82, 83. Hereinafter, only the B pictures marked with arrows in FIG. 12 will be described.
Initially, the B picture B4 will be described. When the B picture B4 originally recorded on the magnetic tape 17 of the recording-side VCR 10 is restored, as shown by arrows in FIG. 12G, the I picture I3 originally recorded on the magnetic tape 17 of the recording-side VCR 10 and the I picture I2' newly recorded by the insert edition are used. Specifically, the B picture B4 is restored by using the I picture I3 used when the B picture B4 is coded and the I picture I2' as the insert image having no relation to the B picture B4.
Subsequently, a B picture B3' newly recorded by the insert edition will be described. When the B picture B3' newly recorded by the insert edition is restored, as shown by arrows in FIG. 12, the I picture I2' newly recorded by the insert edition and the I picture I4' newly recorded by the insert edition are used. Specifically, the B picture B3' is restored by using the I picture I2' used when the B picture B3' is coded and the I picture I4' used when the B picture B3' is coded.
A B picture B5' newly recorded by the insert edition will be described. When the B picture B5' newly recorded by the insert edition is restored, as shown by arrows in FIG. 12G, the I picture I4' newly recorded by the insert edition and the I picture I9 originally recorded on the recording tape 17 of the recording-side VCR 10 are used. Specifically, the B picture B5' is restored by using the I picture I4' used when the B picture B5' is coded and the I picture I9 which is originally recorded on the recording tape 17 of the recording-side VCR 10 and has no relation to the B picture B5'.
As understood from the above description, when the interframe-coded insert images recorded on the magnetic tape 17, interframe-coded image data at an insert start point and interframe-coded image data at an insert end point are restored by using images which are not used when the interframe-coded image data are interframe-coded. In FIG. 12G, such interframe-coded image data are the B picture B4 originally recorded on the magnetic tape 17 of the recording-side VCR 10 and the B picture B5' newly recorded by the insert edition on the magnetic tape 17 of the recording-side VCR 10.
Accordingly, as shown in FIG. 12I, of restored reproduced images V0B to V11I, a reproduced image V4B based on the B picture B4 originally recorded on the magnetic tape 17 of the recording-side VCR 10 and a reproduced image V5B' based on the B picture B5' newly recorded by the insert edition on the magnetic tape 17 of the recording-side VCR 10 are images whose picture qualities are remarkably deteriorated since the images are decoded by using two images having no relation with each other.
For example, if image data originally recorded on the magnetic tape 17 of the recording-side VCR 10 are image data indicating a mountain and image data newly recorded by the insert edition are image data indicative of sea, then the "image whose picture quality is remarkably deteriorated" is an image restored by using the image data indicating a mountain and the image data indicating sea. The image may be referred to as "an image which cannot be visually identified by wrong processing" rather than "an image whose picture quality is remarkably deteriorated".
While such disadvantage is caused in the bidirectionally predictive coding as described above, such disadvantage is similarly caused in one-direction predictive coding. For example, although the B picture B4 shown in FIG. 12G is coded by using an I picture I4 (which is not shown in FIG. 12G because of overwriting due to the insert edition), the B picture B4 is restored by using the I picture I2' newly recorded by the insert edition on the magnetic tape 17 of the recording-side VCR 10. Although the B picture B5' shown in FIG. 12G is coded by using an I picture I6' (which is used upon the coding and only a small amount of data of which is recorded on the magnetic tape 17 of the recording-side VCR 10), the B picture B5' is restored by using the I picture I9 originally recorded on the magnetic tape 17 of the recording-side VCR 10 as shown in FIG. 12G. Specifically, even when the one-direction predictive coding is carried out, it is inevitable to reproduce the image whose picture quality is remarkably deteriorated.
A word "frame" will be defined. When an image is a picture object picked up by a video camera, the "frame" is formed of odd and even fields in television systems such as NTSC system, PAL system or the like. When an image generated by a processing of computer graphics, the "frame" is an image generated by using one frame. While the problem caused when a "frame" image is handled is described above, the problem is, strictly speaking, not a problem caused when the "frame" image is handled but a problem when a coding processing is effected on images at different positions on time base. Thus, when the coding processing is effected on an image obtained by image pickup using a video camera, the above-mentioned problem is similarly caused. When the coding processing is effected on the image generated by the processing of the computer graphics, the image is generally generated by a frame unit in the processing of the computer graphics so that the interframe coding processing is used as the coding processing. Accordingly, when the coding processing is effected on the image generated by the processing of the computer graphics, the above-mentioned problem is caused in the interframe coding processing.